The present invention relates to a device for recovering a synchronized clock signal from a random signal sequence. The device includes a clock generator which generates clock signals whose phase and frequency are tuned to the specific phase and frequency of the signal sequence, wherein the frequency in Hertz, hereafter referred to as f.sub.0, equals the numerical value of the Band of the signal sequence. The clock generator is triggerable externally by specific signals derived from the signal sequence in order to synchronize its phase and frequency with the phase and f.sub.0 of the signal sequence.
In digital data transmission systems, clock pulses synchronized to the data stream received at the end of the transmission path are required to make a decision as to the digital state of each received data bit. The timing recovery from the data arriving in the receiver, which are random sequences, therefore constitutes an important requirement.
For timing recovery, so-called phase-locked loop (PLL) circuits or resonant circuits can be used, which however, are both expensive and only function properly when there are enough transitions between the two digital states of the incoming bit stream. This can be achieved by using suitable scramblers/descramblers.